Jitter-free triggering circuit



. 22, 1910 M. R. KAUFMAN JITTER-FREE TRIGGERING CIRCUIT 5 Sheets-Sheet lFiled March 15, 1968 Sept. 22, 1970 M. R. KAUFMAN 43,530,315

JITTERFREE TRIGGERING CIRCUIT Filed March 15, 1968 ."5 Sheets-Sheet 2FIG. 3

INPUT las TIME

MUR LAN R'. KAUFMAN INVENTOR BY BUCKHORN, BLORE, KLARQLIIST 8. SPARKMANATTORNEYS Sept. 22. 1919 M. R. KAUFMAN 3,530,313 l JITTER-FREETRIGGERING CIRCUIT Filed March 15, 1963 3 3 sheets-sheet 3 V JITTER-FREETRIGGERING CIRCUIT F IG AZO

HOLDOFF CIRCUIT TRIGGER SIGNAL OUT MURLAN R. KAUFMAN IN VEN TORBUCKHORN; BLORE, KLARQUIST 8. SPARKMAN ATTORNEYS 3,530,315 JITTER-FREETRIGGERING CIRCUIT Murlan R. Kaufman, Portland, Oreg., assignor toTektronix, Inc., Beaverton, Oreg., a corporation of Oregon Filed Mar.15, 1968, Ser. No. 713,451 Int. Cl. H03k 3/315 U.S. Cl. 307-286 25Claims ABSTRACT OF THE DISCLOSURE In a circuit for triggering anoscilloscope, an input triggering signal is detected by a first bistabledevice at the conclusion of a sweep holdoff period. Steering circuitmeans intercouples this first bistable device with a second bistabledevice whereby operation of the first device in response to detection ofa triggering signal diverts current to the second in order to establisha triggering condition for the second. A delay means also couples theaforementioned triggering signal to the second bistable device, so thatafter the second bistable device is stabilized, the delayed triggeringsignal is supplied thereto and causes the second bistable device toprovide an output.

BACKGROUND OF THE INVENTION In an oscilloscope device for portraying arepetitive waveform, the term jitter refers to the movement of theportrayed waveform as triggering of horizontal deflection or the like isinaccurately accomplished. In many oscilloscope devices, for example, atriggering signal is derived from the repetitive input waveform forapplication to the devices sweep generator. This triggering signalcauses the sweep generator to produce the horizontal time base, e.g.,the movement of an electron beam from the left side to the right side ofa cathode ray tube screen. The horizontal sweep is successivelytriggered in a correct relation to each repetition of an input waveformsuch that the portrayed waveform appears in substantially the same placeon a cathode ray tube screen for each successive trace. However, if thesweep generator does not initiate its swep output for applciation to thehorizontal defiection plate in accurately timed relation with successivetriggering signals, jitter or movement of the portrayed waveform islikely to result.

After each sweep waveform is generated by a sweep generator, the sweepgenerator must recover -before another sweep waveform is generated. Forthis purpose, the horizontal sweep system is appropiately provided witha holdoff circuit which disables the sweep generator until the latter iscapable of providing an accurate sweep waveform. A holdoff signal isproduced by the holdoff circuit and is conventionally used to inhibitthe sweep generator. Both the holdoff signal and triggering signals maybe applied to the sweep generator in an opposing sense. Then when theholdofi voltage declines sufiiciently, a triggering signal may againinitiate a horizontal sweep.

A principal source of jitter takes place if a triggering signal isreceived when the holdoff has almost, but not quite, recovered. As aresult, the triggering signal may or may not cause the production of asweep output at a desired time. Furthermore, since both the holdoffsignal and the triggering signal are effectively applied as inputs to asweep generator, different portions of a triggering signal may cause theinitiation of a sweep output, depending upon the actual value of theholdoff signal that may be present at the time triggering isaccomplished.

In the copending application of I ames H. Knapton and Henry A.Zimmerman, U.S. application er. No. 713,- 452, entitled, litter-FreeTriggering Method and Appara- @nited States Patent O "ice Patented Sept.22, 1970 tus, and assigned to the assignee of the present invention, amethod and apparatus is disclosed for reducing jitter in a triggeringoperation, lwhich might otherwise be occasioned at the end of a holdoffperiod. In the circuit therein disclosed and claimed, a rst bistablemeans, which may comprise a tunnel diode, is employed to detect an inputtriggering signal. The first means is coupled through an amplifier to asecond bistable means, `which may comprise a tunnel diode, to thereuponestablish a triggerable condition rfor the second bistable means. Adelayed version of the same triggering signal is also applied to thesecond bistable means and triggers the second bistable means after adefinite triggerable condition has been established therefor. Theaforementioned circuit, while quite efficacious in eliminatingtriggering jitter, nevertheless has certain speed limitations occasionedby the delay in the amplifier coupling the bistable means. Aconventional amplifier coupling means between tunnel diodes, forexample, usually does not operate at a speed commensurate with thecapabilities of tunnel diodes, and therefore extra delay occurs beforethe sweep begins. As a result, the first part of a triggering waveformmay not be present in the oscilloscope presentation, or extra delaymeans must be added to the oscilloscopes vertical amplifiers. Suchadditional delay means may cause distortion in the waveform displayed.

SUMMARY OF THE INVENTION According to the present invention the inputtriggering signal is detected in a first bistable circuit or device atthe conclusion of the holdoff signal, and this device is employed toestablish a triggerable condition for a second bistable circuit ordevice. Then, the triggering signal, preferably as delayed, is appliedto the second bistable device for providing a triggering signal output.According to the present invention a current steering circuit isutilized for directly coupling the bistable devices. This steeringcircuit first provides a given current to the first bistable device, andas a consequence of detection in the first device, current is steered tothe second bistable device for establishing a predetermined triggerablecondition therefor. It has been found that the triggering level for thesecond device can then be established in approximately a nanosecondafter the aforementioned detection, resulting in more rapid triggeringand a shorter delay between occurrence of the input triggering signaland the initiation of another triggering output.

It is accordingly an object of the present invention to provide animproved and fast acting circuit for triggering oscilloscope operationsubstantially without the jitter which frequently occurs at the end of aholdoff period.

Another object of the present invention is to provide an improved fastacting trigger circuit for an oscilloscope or the like which issubstantially automatic in its operation, over a wide frequency range,and which provides reliable, jitter-free triggering.

The subject matter which I regard as my invention is particularlypointed out and distinctly claimed in the concluding portion of thisspecification. The invention. however, both as to organization andmethod of operation together with further advantages and objectsthereof, may best be understood by reference to the followingdescription taken in connection with the accompanying drawings whereinlike reference characters refer to like elements.

DRAWINGS FIG. l is a block diagram of a jitter-free triggering circuitaccording to the present invention;

FIG. 2 is a schematic diagram of the same circuit;

FIG. 3 is a first waveform chart illustrating operation of the presentinvention;

FIG. 4 is a second and more detailed waveform chart illustratingoperation of the present invention; and

FIG. 5 is a schematic diagram of a second jitter-free triggering circuitaccording to the present invention.

DETAILED DESCRIPTION Referring to FIG. l, a Schmitt circuit receivesinput triggering signals at 12 and provides a shaped output at 14 forapplication to both first bistable device 16 and delay line 18. Aholdoit circuit also provides an input current to bistable device 16through arming current delay 22, the holdoif circuit having beenoperated by an oscilloscope sweep generator or the like. Holdoif circuit20 further provides an input current to second bistable device 26 aswell as a source of current to steering circuit 28. Steering circuit 28,which substantially directly couples device 16 to device 26, alternatelysupplies such current to bistable device 16 or bistable device 26,according to the state and bias of these devices. The output of delayline 18 is applied to bistable device 26 for operating the same toprovide a trigger signal output. The trigger signal output may initiateoperation of an oscilloscope horizontal sweep ramp generator or a rampcircuit in a sampling oscilloscope. The circuit may alternatively drivea pulse generator or some other triggerable device.

Holdoif circuit 20 may be operated either by detecting a voltage whichthe output of a sweep generator will reach, or else the holdoif circuitmay be operated at some other time, for instance by timing circuitrywhich causes holdoff circuit 20 to assume a diiierent output state whenthe circuitry has recovered from a prior triggered operation. Theholdoff circuit in the present example provides a holdoff signal whichcontinues for the duration of a holdoff period, the latter equalling atleast the recovery time of the circuitry.

The FIG. 1 circuit operates in the following manner. At the conclusionof the holdof signal generated by holdoff circuit 20, current issupplied from the holdoff circuit to bistable device 16 through armingcurrent delay 227 as well as to the steering circuit 28. The applicationof current to device 16 is delayed as a result of the presence of armingcurrent delay 22. Holdoff circuit 20 supplies an initial current tobistable device 26, and steering circuit 28 initially provides itscurrent to bistable device 16. The two currents supplied device 16together render device 16 responsive to a triggering signal from Schmittcircuit 10, substantially at the end of a holdoff signal, that issubstantially at or after the conclusion of the holdoff period, andafter the delay of arming current delay 22.

Bistable device 26 represents means in which a triggerable condition isestablished for a ramp generator or other device to which the triggersignal output is applied. When bistable device 16 receives an inputtriggering signal from Schmitt circuit 10 at the conclusion of a holdoffperiod, it switches from a iirst stable state to a second stable state,causing the current supplied by steering circuit 28 to be shifted frombistable device 16 to bistable device 26. The current supplied directlyfrom the holdoff circuit to bistable device 16 continues to flow to keepbistable device 16 in its second stable state. The shifted current, inaddition to the current initially provided bistable device 26 fromholdoff circuit 20, establishes a triggerable condition for bistabledevice 26 corresponding to a rst state thereof.

Delay line 18 also receives the same input triggering signal fromSchmitt circuit 10 and provides a delayed triggering output forapplication to bistable device 26. If bistable device 26 is now intriggerable condition, the device 26 is switched from a rst stable statethereof to a second stable state for operating a device to which thetrigger signal output is connected, e.g. a horizontal sweep circuit orthe like of an oscilloscope. Since bistable device 26 has had time toreach a rst stable state or a stabilized triggerable condition beforethe application of such delayed triggering signal via delay line 18,triggering is certain and timed correctly in the saine relation to atriggering signal for each successive triggered operation.

The bistable device 16, which arms bistable device 26 at the end of theholdoif period, may be subject to differences in the time of operationfrom one triggered operation to the next. However, the delay of delayline 18 is arranged to be such that, in any case, the steering circuit28 as operated by bistable device 16 will have switched current tobistable device 26 for establishing a stable triggering conditiontherefor in advance of the receipt of the delayed triggering signal fromdelay line 18. As a result, triggered operation of a driven device,e.g., the detiection means, occurs accurately and substantially withoutjitter.

The circuit according to the present invention, employing a currentsteering circuit between bistable devices 16 and 26, enables rapidarming of bistable device 26 by bistable device 16 so that the operatingspeed of the circuit is quite fast. The current switching in the currentsteering circuit can take place in about a nanosecond. The delay indelay line 18 is suitably several nanoseconds, for example, 5nanoseconds, to insure that the triggerable condition of bistable device26 is firmly established before the delayed triggering signal is appliedthereto. In addition, arming current delay 22 is interposed betweenholdoff circuit 20 and bistable device 16 to insure that the currentinitially directly provided from holdoif circuit 20 to bistable device26 is lirmly established before bistable device 16 is rendered receptiveto a triggering signal from Schmitt circuit 10.

The Schmitt circuit 10 is advantageously employed to provide atriggering output at 14 for a fairly wide range of inputs at 12. It isunderstood that various other circuits may be substituted therefor, forexample, a multivibrator triggered by a triggering input signal. yIn thelatter case, a holdotf signal fro-m holdoff circuit 20 is also suitablyprovided to such multivibrator to inhibit operation thereof during theholdof period.

IReferring to the schematic diagram of FIG. 2. wherein like referencenumerals refer to like elements, the input triggering signal is againreceived at 12 and is coupled through resistor 30 to the emitter of PNPtransistor 32 to which a supply current is also delivered. The base oftransistor 32 is also connected to a Source of current and through diode34 to ground. The cathode of diode 34 is connected to the base oftransistor 32 and this diode is employed for maintaining the base of thetransistor at a predetermined voltage level. Transistor 32 provides anisolation stage for the circuitry according to the present invention.The transistor stalge configuration is essentially that of a common baseamplifier, with the collector of transistor 32 being connected to theanode of a negative resistance device, e.g. tunnel diode 36.

Negative resistance `device or tunnel diode 36 forms the principalcomponent of Schmitt circuit 10 and is coupled between the collector oftransistor 32 and a negative voltage point. An inductance 38 connectsthe anode of tunnel diode 36 to a shunting circuit comprising resistor40 in series with the collector-emitter path of NPN transistor 42. Theemitter of transistor 42 is connected to the cathode of tunnel diode 36,and the base of transistor 42 is connected to a source of current. Thejunction between inductance 318 and resistor 40` is coupled to the anodeof a diode 44 by means of resistor 46, while the anode of diode 44 isalso connected to a source of current, its cathode being returned to thecathode of tunnel diode 36.

The circuit 10 including tunnel diode 36 operates in a manner of aSchmitt trigger wherein tunnel diode 36 normally resides in a lowvoltage state. When an input at 12 exceeds a first value, tunnel diode36 switches to a second state, exhibiting a relatively high voltagethereacross as long as the input remains above such level. Then, whenthe input at 12 drops below a second and lower level, diode 36 returnsto its low voltage condition. The circuit thus exhibits a hysteresischaracteristic. This characteristic is narrowed by shunting the tunnel`diode with a resistance here comprising transistor 42 in series withresistor 40. Moreover, transistor 42 is operative to present a firstvalue of resistance when tunnel diode 36 is in its high voltage state,whileexhibiting a higher value of resistance when the tunnel diode is inits low voltage state, whereby less initial triggering current is takenby transistor 42. The circuit including diode 44 is a temperaturecompensating circuit coupled essentially in parallel with the tunneldiode. The diode `44 draws a changing current with temperature in themanner similar to the action of tunnel diode 36 for compensating thesame. The output voltage across `diode 36 is illustrated in FIG. 3 asV36.

The output of tunnel diode 36 is differentiated by a capacitor 48 andcoupled :from the anode of tunnel diode 36 via capacitor 48 in serieswith resistor 50 to the anode of another negative resistance device,e.g. tunnel diode 52, the cathode of which is returned to a negativevoltage point. This negative resistance device or tunnel diode herecomprises the bistable device 16. The output of tunnel diode 36 is alsodifferentiated by means of capacitor 54 in series with resistor 56coupling the anode of tunnel diode 36 to the input of delay line 18.Delay line 18 is suitably a 50 ohm coaxial line having a delay ofapproximately 5 nanoseconds, and its output is coupled to the anode oftunnel diode 68 through resistor 24. Differentiated pulses indicated at57 and 59 in FIG. 3 are therefore substantially identically delivered toboth tunnel diode y52 and delay line 18, coincident with the beginningand end of a voltage square wave across tunnel diode 36, indicated atV36 in FIG. 3.

The output of holdoff circuit is connected to the base of PNP transistor58, the emitter of which is conne'cted to a positive voltage. Thecollector of transistor S8 is coupled through a series connectioncomprising resistors 60 and 62 in that order between the collector oftransistor 58 and the anode of tunnel diode 52., while a capacitor 64 isconnected from the midpoint of the resistors to ground. Resistors 60 and62 together with capacitor 64 form an arming current delay circuit 22.

The collector of transistor S8 is also coupled through resistor 66 tothe anode of a negative resistance device, here comprising tunnel diode68. Tunnel diode 68 in this circuit comprises the bistable device 26,and its cathode is returned to a negative voltage point through biasresistor 7 0.

A source of current is applied at 72 to flow through resistor 70 andthus provide a voltage drop biasing the cathode of tunnel diode 68positive relative to the cathode of tunnel diode 52. The anode of tunneldiode 68 is also connected to the output of delay line 18, as well as tothe trigger signal output.

Between tunnel diode 52 and tunnel diode 68 is located a currentsteering circuit I28 here comprising a resistor 74 coupled between thecollector of transistor 58 and the anodes of Schottky barrier diodes 76and 78. The cathode of diode 76 is connected to the anode of tunneldiode S2 while the cathode of diode 78 is connected to the anode oftunnel diode 68. During a given state of holdoff circuit 201, at theconclusion of a holdoff period, a current of approximately 6milliamperes is provided at the collector of transistor 58` throughresistors 60 and 62- to tunnel diode 52. Application of this current isdelayed somewhat by the combination of resistors 60 and 62, andcapacitor 64. Also, a similar amount of current, e.g. 6 milliamperes, isprovided through resistor 66 to tunnel diode 68. In addition, a currentof approximately 3 milliamperes is suitably provided through resistor 74to the anodes of diodes 76 and 78. The latter current initially flowssubstantially entirely through tunned diode 52, when the circuit isuntriggered, since the cathode of tunnel diode 68 is biased by resistor7 0, biasing the cathode of diode 78 such that the latter does notconduct. The foregoing currentdistribution takes place before thecircuit is triggered.

Assume now that a prior trigger signal output has just been delivered,and holdoff circuit 20 is operated by a sweep generator or the like toprovide a positive-going holdoff signal for a predetermined holdoff orcircuit recovery period. The holdoff signal from holdoff circuit 20during this period substantially cuts off transistor 58 so that theaforementioned currents through resistors 60 and 62, resistor 74, andresistor 66 are not provided. At the conclusion of the holdoff period,the holdoff signal from holdo circuit 20 concludes, allowing transistor58 to conduct and again provide these currents. It is understood thatthe values of currents given are by way of example only for purposes ofillustrating the operation of the present invention. It is alsounderstood that when a detection or some other function is spoken of ashappening at the conclusion of a holdoff period or holdoff signal, it ismeant that such occurrence may take place substantially at the end ofsuch period or signal, or at any time thereafter.

Operation of the FIG. 2 circuit will be explained with the aid of theFIG. 3 waveform chart. The FIG. 3 chart assumes that a prior triggeredoperation has just taken place, and a vertical line 80 indicates the endof a holdoff period. At this time, a current of 6 milliamperes isimmediately provided tunnel diode 68 as indicated at 82 in FIG. 3, and acurrent of 3 milliamperes is substantially immediately provided totunnel diode 52 through diode 76 as indicated at 84 in FIG. 3. A furthercurrent of 6 milliamperes is supplied to tunnel diode 52 throughresistors 60 and 62 as indicated by the slowly rising curve at 86, butthe full application of this current is delayed as a result of the timeconstant of the arming current delay circuit 22, including resistors 60and 62, and capacitor 64. Now, it is assumed an input is received forproviding the aforementioned differentiated signal 57 correspondingsubstantially to the start of such input. The first occurrence of suchinput may produce such a differentiated signal 57 superimposed upon theslowly rising portion 86 of the 152 current waveform. This signal doesnot exceed the triggering level 88 which would switch tunnel diode 52from its low voltage state to its high voltage state. However, after thecurrent of 6 milliamperes through resistors 60 and 62 is fully applied,the next occurrence of differentiated signal 57 exceeds triggering level88, switching tunnel diode 52 to its high voltage state.

Both tunnel diodes 52 and 68 in the present example requireapproximately 10 milliamperes to switch the same from a low voltagecondition to a high voltage condition. As understood by those skilled inthe art, when the proper current is provided, switching takes place veryrapidly. In the situation indicated, at the end of a holdoff period, andafter the delay produced by arming current delay 22, a total of 9milliamperes is delivered to tunnel diode 52 for defining a first statethereof` wherein the tunnel diode is readily triggerable to a second orhigh voltage state by application of a one milliampere or greatertriggering input pulse, for example. Triggering level 88 indicates thelevel which must be exceeded before tunnel diode 52 is switched to itshigh voltage state.

When tunnel diode 52 switches to its high voltage state, the voltage atthe cathode of diode 76 is higher than the voltage at the cathode ofdiode 78, and therefore diode 76 ceases to conduct, as indicated at 90in FIG. 3, and diode 78 starts conduction as indicated at 92. Thecurrent transfer occurs in about a nanosecond. As a result, tunnel diode68 now receives 9 milliamperes, with l0 or more being required in thisexample to switch tunnel diode 68 to its high voltage state. A currentof 6 milliamperes is still provided tunnel diode 52 through resistors 60and 62 to keep tunnel diode 52 in its high voltage state, at least untilthe next holdoff period commences. Thus, tunnel diode 68 by theapplication of the total of 9 milliamperes in this example is armed to afirst or triggerable state. Moreover, the current through the tunneldiode defines a definite triggerable condition requiring the triggeringpulse of a definite and predetermined magnitude for causing tunnel diode68 substantially immediately to assume its high voltage state. In thepresent circuit, this condition or level is fully stabilized beforetriggering is applied to tunnel diode 68. Triggering is actually appliedvia delay line 18 having a delay long enough to insure stabilization ofthe arming current through tunnel diode 68.

The delayed differentiated signals delivered through delay line 18 areillustrated at 94 and 96 in superposition with respect to current 168.ln FIG. 3 D indicates the delay of delay line 18. When tunnel diode 68received only 6 milliamperes, the delayed signal 94 had not reached thetriggering level 98 for tunnel diode 68. However, as the full 9milliamperes are applied, delayed differentiated signal 94 exceedstriggering level 98 causing tunnel diode 68 to assume its high voltagestate. As tunnel diode 68 assumes its high voltage state, a triggersignal output is produced for triggering a horizontal sweep circuit orthe like. Not only does such triggering always occur at a predeterminedtime relative to the input triggering signal, thereby avoiding jitter,but also triggering occurs with a minimum of time delay after theoccurrence of a particular triggering signal because of the rapidswitching afforded by the tunnel diodes and steering circuit 28immediately coupling the tunnel diodes. Therefore, portrayal of thetrigger signal is more rapid, and less delay need be included in theoscilloscopes vertical amplifier section.

FIG. 4 illustrates the jitter--free advantages of the circuit accordingto the present invention, showing the waveforms which exemplify twotriggering situations. The waveforms are referred to by referencenumerals corresponding to those employed in FIG. 3. A iirst situation isillustrated in full lines, while a second situation is illustrated indashed lines. In each instance, the square wave output from tunnel diode36 is shown at V36.

In the tirst instance, shown in full lines, differentiated input 57superimposed on I52 just reaches triggering level 88 to switch currentby means of the current steering circuit from tunnel diode 52 to tunneldiode 68. The current in tunnel diode 68 increases to just belowtriggering level 98, Then, delayed differentiated output 94 is appliedto tunnel diode 68, exceeding its triggering level 98, and causing thetunnel diode 68 to switch to its high voltage state for initiating ahorizontal sweep. The time period from the beginning of the square wavefrom tunnel diode 36 to the time at which tunnel diode 68 begins toreceive current from diode 78 is designated as a. The time period fromthe beginning of the same square wave to the time at which tunnel diode68 switches is designated as b.

In the second situation shown in dashed lines FIG. 4, the early portionof differentiated input S7 reaches triggering level 88 after a timeinterval c from the beginning of the occurrence of the square waveproduced by tunnel diode 36. At such time, current begins switching fromdiode 76 to diode 78 as indicated at 100. Then, after a time interval,d, from the beginning of the square wave produced by tunnel diode 36,the delayed differentiated input exceeds triggering level 98 causing thetunnel diode -68 to switch to its high voltage state and initiate ahorizontal sweep by sweep generator 24. It is observed that time perioda in FIG. 4 is not equal to time period c, but time period b and timeperiod d are equal. Time periods b and d correspond to the delay D inFIG. 3, or the delay of delay line 18. Thus, the time of switching oftunnel diode 52 is variable depending upon the time when the holdoffperiod is concluded in relation to the input signal, and if the outputof tunnel diode 52 were employed directly to trigger a sweep generatoror the like, jitter could result. However, no triggering arises sincethe trigger signal output is derived from tunnel diode 68. It isunderstood that the reception of a triggering signal at the conclusionof the holdotf period is nearly always subject to jitter because theexact time of the occurance of an input triggering signal is unknown bythe triggering circuit, and the conclusion of 8 the holdoif signal doesnot always occur in the same timed relation with respect to the receiptof such input triggering signal.

In the present instance, `tunnel diode 52 quickly provides a triggerablecondition or level for tunnel diode 68 that is fully stabilized beforethe delayed triggering signal arrives via delay line 18 to switch tunneldiode `68 and operate sweep generator 24. Therefore, jitter does notoccur. In the present circuit additional time delay in further avoidanceof jitter is introduced between the holdof'f circuit and the tunneldiode 52 by arming current delay circuit 22 so that the initial 6milliamperes provided tunnel diode 68 through resistor 66 is fullystabilized before 3 milliamperes more current is provided via diode 78.Delay line 18 is arranged to have a delay sufficient for providing thedelayed input trigger signal to tunnel diode 68 after a stable level fordiode 68 is secured. However, in the circuit according to the presentinvention, the delay involved is appreciably less than the delay thatwould be necessary without employment of the steering circuit means.

It is understood that when a holdotf signal again occurs, currents areno longer provided from transistor S8, and tunnel diodes 52 and 68 arereverted to their non-triggered condition.

Another embodiment of the present invention is illustrated in FIG. 5wherein primed reference numerals refer to elements corresponding tothose in FIG. 2. The circuit of FIG. 5 includes a current supplyresistor 74 a first end of which is provided current from holdoffcircuit 20 at the end of a holdoff period, and the remaining end ofwhich is coupled to the anode of tunnel diode 68'. A current steeringresistor 112 is coupled between the anode of tunnel diode 52 and theanode of tunnel diode 68. Current is supplied tunnel diode 52 at the endof a holdoif period through a time delay circuit comprising resistors 60and 62 in series With their midpoint shunted to ground by capacitor 64.The application of this current is thus delayed somewhat relative to theapplication of current through resistor 74'. Additional current is alsoprovided tunnel diode 68' through the series combination of resistor 66'and variable resistor 118. Variable resistor 118 is here employed toadjust the bias on tunnel diode 68.

The FIG. 5 circuit receives a triggering input via terminal 102 which iscoupled by way of capacitor 104 to the anode of tunnel diode 106. Tunneldiode 106 is provided current from holdof circuit 20 at the end of aholdoff period through inductance 108. The opposite end of inductance108 from tunnel diode 106 is returned to ground through load resistor110. Tunnel diode 106 operates as a free running oscillator, exceptduring the holdoif period, having a rst natural frequency, but which istriggered to provide output pulses in synchronism with a triggeringinput applied at terminal 102. Inductance 108 and load resistor 110complete the oscillator circuit. It has been found that the inductance108 is frequently secured by lead inductance alone, so that no actualcomponent part is required. The output at the anode of tunnel diode 106is applied to the anode of tunnel diode 68 through a differentiatingcircuit comprising resistor 114 in series with capacitor 116.

At the end of a holdoff period, i.e. when current is supplied tunneldiode 68', pulses from tunnel diode 106 are insufcient in amplitude toswitch tunnel diode y68 from a low voltage state to a high voltagestate. However, at the conclusion of a holdoif period, sufficientcurrent will be supplied through resistors 60' and 62', with a slightdelay, so that tunnel diode 52 is triggered to its high voltage state bya pulse from tunnel diode 106. At this time, a current is\caused to flowthrough resistor 112 which is steered to tunnel diode 68' as aconsequence of the higher voltage across tunnel diode 52. After theadditional current is supplied tunnel diode 68', the latter will bearmed, and receptive to triggering. A subsequent pulse from tunnel diode106, will then trigger tunnel diode 68 to its high voltage state andproduce a trigger signal output. In the foregoing circuit, variableresistor 118 is adjusted so that tunnel diode 68 is not armed andtriggerable until the further current is provided thereto by thesteering circuit 28'. The delay in the circuit including resistors 60and 62', and capacitor |64', permits initial current through resistors74', 118 and l66 to be stabilized in tunnel diode 68 before additionalarming current is diverted thereto by the steering circuit.

While I have shown and described preferred embodiments of my invention,it will be apparent to those skilled in the art that many changes andmodifications may be made without departing from my invention in itsbroader aspects. I therefore intend the appended claims to cover allsuch changes and modifications as fall within the true spirit and scopeof my invention.

I claim:

1. A jitter-free triggering circuit comprising:

means for providing a holdoff signal during a predetermined holdoffperiod, first bistable means for detecting a given triggering inputsubstantially at the conclusion of said holdoff signal,

second :bistable means in which a triggerable condition is establishedand which initiates a trigger signal output,

current steering means substantially directly coupling said firstbistable means to said second bistable means for initially supplyingcurrent to said first bistable means, wherein the detection of saidgiven tri-ggering input by said first bistable means changes the stateof said first bistalble means and steers current theretofore supplied tosaid first bistable means to said second bistable means for determiningthe triggerable condition for said second bistable means,

delay means for also receiving said triggering input and for delayingthe same,

and means for coupling the triggering input as delayed to said secondbistable means, wherein said triggering signal as delayed changes thestate of the second bistable means, when the latter is in triggerablecondition, for initiating a trigger signal output from said circuit.

2. The circuit according to claim 1 wherein additional current issupplied to said first bistable means at the end of a holdoff period.

3. The circuit according to claim 2 wherein additional current is alsosupplied to said second bistable means at the end of a holdoff period.

4. The circuit according to claim 2 including time constant meanscoupled to said first bistable means for delaying the full supply ofsaid additional current thereto.

5. The circuit according to claim 3 further including time constantmeans coupled to said first bistable means for delaying the full supplyof said additional current to said first bistable means at least untilsuch additional current is substantially fully provided to said secondbistable means.

6. The circuit according to claim 1 wherein said current steering meansis provided current from said means for providing a holdoff signal atthe end of a holdoff period thereof.

7. The circuit according to claim 6 wherein said current steering meanscomprises a pair of diodes receiving current from said means forproviding a holdoff signal at the end of a holdofi period thereof,including a diode coupled to said second bistable means which isinitially biased so that current is initially delivered to said firstbistable means via the other diode before the change of state of saidfirst bistable means.

8. The circuit according to claim 6 wherein said current steering meanscomprises current supply coupling means for providing current to saidbistable means from said means for providing a holdoff signal at the endof a holdoff period, and including means coupling said first bistablemeans to said second bistable means, Iwherein sufficient current issteered to the second bistable means for determining the triggerablecondition thereof only after said first bistable means changes state toa higher voltage condition in response to said given triggering input sothat less current is drawn thereby, in order that greater current isprovided said second bistable means.

9. The circuit according to claim 1 wherein each of said bistable meanscomprises a tunnel diode.

10. A jitter-free triggering circuit comprising;

means for providing a holdoff signal for a predetermined holdoff period,

a first negative resistance device to which said holdoff signal iscoupled for preventing operation of said first negative resistancedevice until the conclusion of said predetermined holdoff period,

means for coupling an input triggering signal to said first negativeresistance device for changing the stable state thereof in response toan input triggering signal at the conclusion of said holdoff period,

a second negative resistance device coupled for providing a triggersignal output,

current steering means intercoupling said first and second negativeresistance devices by means of which a current is initially provided thefirst device at the conclusion of a holdoff period and wherein saidcurrent is steered to the second device when the first device istriggered to a second bistable state, the steered current acting toestablish a triggerable condition for said second device,

delay means for also receiving said input triggering signal and fordelaying the same,

and means for coupling a triggering signal as delayed to said secondnegative resistance device to change the state thereof and provide atrigger signal output.

11. The circuit according to claim 10 further including means forproviding an additional current to said first negative resistance deviceat the end of said holdoff period, which additional current continues tobe supplied for maintaining the changed stable state of said firstnegative resistance device after the diversion of current by saidcurrent steering means.

12. The circuit according to claim 10 wherein said current steeringcircuit comprises a pair of Schottky barrier diodes receiving currentfrom said means for providing a holdoff signal at the conclusion of saidholdoff period;

and biasing means coupled to said current steering circuit for causingthe current from said means for providing a holdofrsignal to be firstprovided to said first negative resistance device until a change ofstate thereof alters its bias to cause current to flow to the secondnegative resistance device, thereby establishing a triggerable conditionfor the second device.

13. The circuit according to claim 12 further including means forproviding an additional current from said means for providing aholdoff'signal at the end of said holdoff period to both the first andsecond negative resistance devices, and time constant means coupled tothe first such device whereby the additional current rises first in thesecond device.

14. The circuit according to claim 10` wherein said negative resistancedevices each comprise tunnel diodes.

15. The circuit according to claim 10 including a Schmitt circuitcoupled to provide said input triggering signal to said first negativeresistance device and to said delay means, said Schmitt circuitcomprising a third negative resistance device for shaping a triggeringinput provided thereto.

16. The circuit according to claim 15 wherein said third negativeresistance semiconductor device comprises a tunnel diode and furtherincluding a semiconductor device having its principal current carryingpath coupled across said tunnel diode and biased for conducting lightlywhen said tunnel diode is in a low voltage state, while con- 1 1 ductingmore heavily when said tunnel diode is in a high voltage state.

17. A jitter-free triggering circuit comprising:

means for providing a holdoff signal during a predetermined holdoffperiod, first bistable means for detecting a given triggering inputsubstantially at the conclusion of said holdotf signal,

second bistable means in which a triggerable condition is establishedand which initiates a trigger signal out- Put,

currrent steering means substantially directly coupling said firstbistable means to said second bistable means for initially supplying aiirst current to said rst bistable means, wherein the detection of saidgiven triggering input by said iirst 'bistable means changes the stateof said first bistable means and steers current theretofore supplied tosaid rst bistable means to said second bistable means for determiningthe triggerable condition for said second bistable means.

means for providing additional current to said time constant means witha delay relative to the supply of said first current,

and means for coupling a triggering signal to said second bistablemeans, wherein said triggering signal changes the state of the secondbistable means, when the latter is in triggerable condition, forinitiating a trigger signal output.

18. The circuit according to claim `17 including delay means forreceiving said triggering input, said triggering signal comprising saidgiven triggering input as delay by said delay means.

19. The circuit according to claim 17 wherein said triggering signalcomprises a triggering input subsequent to said given triggering input.

20. The circuit according to claim 17 wherein said cur- CTI rentsteering circuit comprises current supply coupling means for providingsaid first current to said devices, and means coupling said devices,wherein a change in state of the rst device is characterized by anincrease in voltage thereacross causing an increase in current to saidsecond device.

21. The circuit according to claim 20 wherein said first current issupplied from said means for providing a holdoff signal.

22. The circuit according to claim 17 wherein said current steeringmeans comprises a pair of diodes receiving said first current from saidmeans for providing a holdof signal.

23. The circuit according to claim 21 wherein said additional current isalso provided from said means for providing a holdoif signal.

24. The circuit according to claim 22 wherein said additional current isalo provided from said means for providing a holdoff signal.

2S. The circuit according to claim 17 including a triggered tunnel diodeoscillator coupled to provide said triggering input.

References Cited UNITED STATES PATENTS 3,215,948 11/1965 Dalton 328-181X 3,339,088 8/1967 Dillard 307-228 X 3,344,285 9/1967 IFrye 307-2283,358,159 12/1967 Smith 307-228 3,350,576 10/ 1967 Zimmerman 307-273 XJOHN S. HEYMAN, Primary Examiner U.S. Cl. X.R.

